A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having multilevel copper wiring layers and its manufacture method.
B) Description of the Related Art
The integration degree and operation speed of large scale integrated circuits are becoming increasingly high. As the integration degree becomes higher, semiconductor elements such as transistors constituting an integrated circuit is made more compact. A compact semiconductor element improves the operation speed. A delay time by wiring regulates the operation speed of a large scale integrated circuit. A wiring delay time depends on the wiring resistance and parasitic capacitance. Reducing the wiring resistance and parasitic capacitance is desired.
Low resistance of wiring is realized by the main wiring material of Cu having a lower resistance than Al. Wiring material having a resistance lower than Cu is practically difficult.
As semiconductor elements are made fine, the number of semiconductor elements fabricated on one semiconductor chip increases. The number of wiring lines is increased in order to interconnect a number of semiconductor elements. As the number of power supply lines and signal lines increases, the number of wiring layers increases. High density of wiring lines increases a wiring capacity.
In order to shorten a wiring delay time, the wiring capacitance is required to be lowered. The material of interlayer insulating films for conventional Cu wiring layers is silicon oxide, F-doped silicate glass (FSG) or the like. An interlayer insulating film made of material having a smaller specific dielectric constant is desired to lower the wiring capacitance.
In order to lower a wiring capacitance, organic insulating material having a low specific dielectric constant has been proposed as the material of an interlayer insulating film. One example of organic materials, SILK (Trademark: Dow Chemical), has a specific dielectric constant of 2.65. As compared to SiO2 having a specific dielectric constant of 4.2, the capacitance can be lowered by about 40%.
After organic insulating material is coated in a liquid state, it is necessary to perform heat treatment at a temperature of about 400° C. for example. Organic insulating material has generally a large thermal expansion coefficient. The thermal expansion coefficient of SiO2 is about 0.6 ppm, whereas that of SILK is about 69 ppm. After the heat treatment is performed to form an insulating film, large tensile stress is generated at a room temperature.
FIG. 2 shows an example of the structure of a large scale integrated circuit having interlayer insulating films made of organic insulating material. In the surface layer of a silicon substrate 10, an element separation trench is formed and insulating material such as silicon oxide is embedded to form a shallow trench isolation (STI) 11. On the surface of an active region defined by STI, a gate G of a MOS transistor is formed. In this way a transistor is formed. Necessary ions are implanted into the silicon substrate and other necessary processes are performed.
On the surface of the semiconductor substrate 10, an insulating layer 18 of a silicon oxide series such as phosphosilicate glass (PSG) is formed. Contact holes are formed and conductive material is filled in to form conductive plugs 19. After the surface of the insulating film is planarized, an SiC layer 20, a SILK layer 22 and an SiC layer 23 are laminated to form a first interlayer insulating film. For example, the SiC layer 20 is about 50 nm thick, the SILK layer 22 is about 450 nm, and the SiC layer 23 is about 50 nm. In this interlayer insulating film, wiring trenches and via holes for connection to the underlying wiring layer are formed and a first wiring layer 29 made of copper as its main component is embedded.
After the surface of the first interlayer insulating film is planarized, an SIC layer 30, a SILK layer 32 and an SiC layer 33 similar to those described above are formed to form a second interlayer insulating film. In the second interlayer insulating film, wiring trenches and connection via holes are formed and a second wiring layer 39 made of copper as its main component is embedded. Similarly, a third interlayer insulating film is formed by a lamination of an SiC layer 40, a SILK layer 42 and an SiC layer 43 and a third wiring layer 49 is embedded. A fourth interlayer insulating film is formed by a lamination of an SiC layer 50, a SILK layer 52 and an SiC layer 53 and a fourth wiring layer 59 is embedded. An SiC layer 60 is formed on the surface of the fourth wiring layer as a copper diffusion preventing layer.
With this structure, peel-off or separation is likely to occur between the lower layers of the interlayer insulating films, i.e., copper diffusion preventing SiC layers 20, 30, 40 and 50 and the overlaid organic insulating resin layers 22, 32, 42 and 52. If the number of wiring layers is increased, separation is more likely to occur.
Separation does not occur between the SiC layer used as a hard mask and the underlying organic insulating resin layer. This may be ascribed to an improved surface quality of the organic insulating resin layer because the surface is exposed to plasma when the SiC layer is formed by plasma CVD.